In manufacturing of semiconductor devices, a photolithographic technique is used for forming a circuit pattern on a semiconductor wafer (hereinafter referred to simply as “wafer”) as a substrate to be processed. In order to form a circuit pattern by using the photolithographic technique, there is performed a patterning process including, applying a resist onto a wafer to form thereon a resist film; irradiating light to the resist film such that the resist film is exposed correspondingly to the circuit pattern, and developing the resist film.
In terms of the recent trend of higher degree of integration of semiconductor devices with a view to improving the operation speed and the like, the photolithographic technique is required to further miniaturize a semiconductor circuit to be formed on a wafer. As the photolithographic technique capable of achieving a high resolution of 45 nm node, there has been proposed an immersion exposure that supplies an exposure liquid, such as deionized water, which has a refractive index higher than air, into a space between a wafer and a projection lens for exposure, thereby reducing a wavelength of light incident from the projection lens with the use of the high refractive index of the exposure liquid, so as to narrow the exposed line width. However, it is difficult to achieve the high resolution of 45 nm node only by the immersion exposure. Thus, with a view to achieving the high resolution of 45 nm node, it is under study that the immersion exposure technique is combined with a technique called double-patterning that forms a fine pattern by twice performing a pattering process including a resist application, an exposure, and a development.
The double-patterning is used for forming a fine resist pattern for etching a layer to be etched which is formed on a wafer. Namely, before the etching that etches the layer to be etched is performed, there is twice performed a patterning process employing the photolithographic technique and including a resist application, an exposure, and a development. A first patterning including a first resist application, an exposure, and a development is performed to form a first resist pattern of a first pitch. Then, a second patterning including a second resist application, an exposure, and a development is performed to add an additional resist pattern to spaces in the first resist pattern. Thus, a resist pattern of a pitch that is approximately a half of the first pitch can be formed as a whole. In order to perform the second patterning, it is necessary to perform a second resist application to the wafer, on which the first resist pattern is formed and which thus has a stepped surface (see, JP2008-281825A, for example).
When the second resist application is performed to the wafer that has been subjected to the first patterning, there arises the following problem.
When the second resist application is performed to the wafer that has been subjected to the first patterning, it is difficult to achieve a flat surface of the resist film due to the stepped surface of the first resist pattern formed by the first patterning.
Unless the resist film is flat, since optical path distances of the irradiated exposure light are different between the center portion of a space in the first resist pattern and the edge portion of the same, the line width of the pattern formed by the second patterning cannot have designed dimensions.
In addition, the fact that the resist film is not flat means that the resist film thickness formed by the second patterning is not uniform within the wafer plane. In-plane non-uniformity of the resist film thickness will result in in-plane non-uniformity of the line width of the pattern formed by the second patterning.